As Tokyo Tech scientists report, the new phased array transmitter design overcomes common problems with CMOS technology in the 300 GHz band. Thanks to its remarkable area efficiency, low power consumption, and high data rate, the proposed transmitter can pave the way for many technical applications in the 300 GHz band, including body and cell monitoring, radar, 6G wireless communications, and include terahertz sensors.

Today, most frequencies above the 250 GHz mark remain unallocated. Accordingly, many researchers are developing 300 GHz transmitter/receivers to take advantage of the low atmospheric absorption at these frequencies, as well as the potential for very high data rates that come with it.

However, high-frequency electromagnetic waves are weakened at high speeds when traveling through vacuum. To overcome this problem, the transmitter must compensate by obtaining a larger effective radiated power. Although some interesting solutions have been proposed over the past few years, no 300 GHz-band transmitter manufactured by conventional CMOS processes has been able to simultaneously realize high output power and small chip size.

Now, a research led by Professor Kenichi Okada of Tokyo Institute of Technology (Tokyo Tech) and NTT Corporation (Headquarters: Chiyoda-ku, Tokyo; President and CEO: Akira Shimada; “NTT”) The team recently developed the 300 GHz band. A transmitter that solves these problems through several key innovations. Their work will be presented at the 2024 IEEE International Solid State Circuits Conference (ISSCC).

The proposed solution is a phased array transmitter consisting of 64 radiating elements, arranged in 16 integrated circuits with four antennas. Since the elements are arranged in three dimensions by stacking printed circuit boards (PCBs), this transmitter supports 2D beam steering. Simply put, the transmitted power can be aimed vertically and horizontally, allowing for fast beam steering and efficient tracking of receivers. In particular, the antennas used are Vivaldi antennas, which can be implemented directly on-chip and have a suitable shape and emission profile for high frequencies.

An important feature of the proposed transmitter is its power amplifier (PA)-end architecture. By placing the amplification stage before the antenna, the system only needs to amplify signals that have already been conditioned and processed. This leads to higher efficiency and better amplifier performance.

The researchers also addressed some of the common problems that arise with conventional transistor layouts in CMOS processes, namely high gate resistance and large parasitic capacitance. They improved their configuration by adding additional drainage channels and vias and by changing the geometry and element between the metal layers. “Compared to standard transistor layouts, parasitic resistance and capacitance are all reduced in the proposed transistor layout,” remarked Professor Okada. “As a result, the transistor gain corner frequency, which is the point where the transistor’s amplification begins to decrease at higher frequencies, was increased from 250 to 300 GHz.”

On top of these innovations, the team designed and implemented a multistage 300 GHz power amplifier for use with each antenna. Thanks to the excellent impedance matching between the stages, the amplifiers showed excellent performance, as Prof. Okada highlighted: “The proposed power amplifiers achieved a gain of more than 20 dB from 237 to 267 GHz, a sharp cutoff with frequency. – turn off unwanted signals.” The proposed amplifier also achieves a noise figure of 15 dB which was evaluated by a noise measurement system in the 300-GHz band.

The researchers tested their design through both simulations and experiments, with very promising results. Notably, the proposed transmitter achieved a data rate of 108 Gb/s in on-PCB probe measurements, which is significantly higher than other state-of-the-art 300 GHz-band transmitters.

Additionally, the transmitter exhibited low power consumption as well as remarkable areal efficiency compared to other CMOS-based designs, highlighting the potential for small and power-constrained applications. Some notable use cases are sixth-generation (6G) wireless communications, high-resolution terahertz sensors, and human body and cell monitoring.