Research introduces mask wafer co-optimization method

At the heart of advancing semiconductor chip technology is a key challenge: making smaller, more efficient electronic components. This challenge is particularly evident in the field of lithography, the process used to create complex patterns on semiconductor materials (called wafers) to manufacture chips.

Lithography uses a type of template, called a photomask or simply a mask, to create patterns on semiconductor wafers. The industry is always looking for methods that improve resolution and manufacturability for both masks and wafers, which will produce faster chips with higher yields of properly functioning chips.

Computational lithography techniques that improve resolution and pattern fidelity, such as optical proximity correction (OPC), have made significant progress in addressing these challenges by modifying individual mask patterns to improve both the mask and the surface. Wafer Printing

Inverse lithography technology (ILT)—a mathematically rigorous inversion approach that determines mask shapes that will produce desired on-wafer results—is a promising solution to many of the challenges of lithography for modern chips. has been seen as Since its introduction more than a decade ago, there have been numerous studies showing that curved ILT mask shapes, in particular, produce the best wafer results.

Until recently, however, the runtimes associated with this computational technique have limited its practical application to critical “hotspots” on chips. In 2019, an entirely new, purpose-built system was proposed, including a unique GPU-accelerated approach that emulates a single, giant GPU/CPU pair that simultaneously The entire full-chip ILT can compute the solution. This new systematically designed approach to ILT and GPU acceleration made full-chip ILT a practical reality in production.

However, this approach relies on multibeam mask writing, a significant new development in mask writing that is pixel-based and thus shape-agnostic in terms of writing time. The question that remained was whether the advantages of full-chip, curvilinear ILTs could be extended to variable-shape beam (VSB) mask writers that write rectilinear (and sometimes triangular) shapes instead of pixels, and that Masks comprise the majority of writers. worldwide today.

While VSB writers create large rectangles by writing one rectangle shot at a time, complex mask patterns can be a problem because writing a large number of small rectangles to create them would take too long.

Their reporting the work I Journal of Micro/Nanopatterning, Materials and MetrologyD2S, Inc. ’s team invented a method called mask wafer co-optimization (MWCO) with three insights: Both the mask writer and the wafer scanner are low-pass filters. Overlapping shots can create curved shapes with fewer shots guided by the mask/wafer simulation. By targeting the wafer pattern, rather than the mask pattern, one can make much easier shots to print the correct wafer pattern. Using this dual simulation, wafer print quality is iteratively optimized while manipulating VSB shot edges to produce rectilinear target mask shapes with a known and acceptable shot count. Known to be writable on the VSB writer.

D2S and Micron Technology have demonstrated that MWCO can reduce wafer variation by up to 3x, and improve the wafer process window by up to 2x compared to Micron OPC, significantly improving the accuracy and reliability of the lithography process. Improvement is indicated. The write time for a full curvature ILT mask will be less than 12 hours, which meets the requirements of high volume production.

This means that all semiconductor manufacturers can now produce chips that are not only smaller, but also more efficient. Low power consumptioneven if they don’t have access to a multi-beam mask writer.